Digital electronics systems and computer systems generally employ a memory subsystem that includes memory devices interfaced to one or more processors/controllers that perform read-write function on the memory devices. Because the speed of operation of processors/controllers is higher than that of the memory subsystem, the operation speeds of such a memory subsystem can always be improved so as to enhance the overall performance of the system.
One of the approaches for improving performance is the use of DDR SDRAM memory devices. The DDR SDRAM enables data to be read and written on both rising and falling edges of the clock cycles, thereby effectively doubling the rate of operation and enhancing performance.
In a DDR memory system, READ and WRITE modes are performed using a data strobe signal (DQS) and a data signal (DQ). The DQS must be aligned at the center of the DQ for successful detection of data. In the WRITE mode, the DQS and the DQ are both sent by an SDRAM PHY such that the DQS is aligned at the center of the DQ while performing the WRITE operation.
However, in the READ mode, because the DQS is not aligned at the center with respect to the data, the DDR PHY (or the memory controller) is required to shift the DQS to the center of the DQ. In a conventional technique, such shifting is normally performed by using a Master-Slave Delay Locked Loop (DLL). A typical configuration of the Master-Slave DLL for shifting the DQS is shown in, for example, FIG. 15. Particularly, a DQS signal is shifted using a Master-Slave DLL and the shifted DQS is then used for capturing the DQ, as shown in FIG. 15. However, the use of such a DLL not only requires additional hardware (such as FIFO circuitry), but also, causes substantial jitters and/or on-chip variations. The use of such a DLL makes it difficult to capture the correct data signal and, thus, is not desirable.
U.S. Pat. Nos. 6,229,759 and 7,679,986 disclose systems for performing WRITE operation on a memory. However, these patents do not solve the problem of capturing the DQ in the READ mode where the DQS is not aligned at the center of the DQ. Further, in the '759 Patent, the DQS is used as a synchronizing signal such that the DQ is sampled with the DQS. However, synchronizing DQ with the DQS requires separating rising and falling edges of the DQS, which requires additional circuitry and logic implementation.
U.S. Pat. No. 8,299,948 discloses a scheme of data capturing using a multiphase clock generating circuit that is required for every bit of data. Such a data capturing scheme is not suitable for a DDR system because it requires ‘k’ number of multiphase clock generating circuits for a k-bit word length memory. Such a scheme not only adds to the circuit area, but also, consumes a lot of power.
One way of extracting the correct DQ sample without using the Master-Slave DLL is discussed in U.S. Pat. No. 7,198,197. This patent discloses how the DQ and the DQS are to be oversampled with a clock signal having a frequency ‘X’ times that of the system clock, where X is an integer. Upon oversampling, this patent employs a method for extraction of correct data on the basis of a defined bit boundary range (BBR). Particularly, the '197 Patent recites a voting scheme on the basis of values of the DQS to determine the DQ. However, the use of this voting scheme also consumes a lot of power and requires a large area on the circuit.
Therefore, even upon implementing such a scheme for data capturing, there still remains an unfulfilled need of capturing correct data with reduced circuitry, power consumption, and area requirements.
In view of the above, there exists a need for data recovery at the DDR PHY in the READ mode in a manner that improves timing margins and substantially reduces jitters and/or distortions. Further, there exists a need for data recovery in a manner that reduces the “overheads,” such as circuit area requirements and power consumption.